1. Field of the Invention
Exemplary aspects of the present invention relate to a semiconductor design support device, a semiconductor design support method, and a manufacturing method, and more particularly, to a semiconductor design support device and a semiconductor design support method for designing a semiconductor integrated circuit and a method for manufacturing the semiconductor integrated circuit.
2. Description of the Related Art
Advances in semiconductor manufacturing technologies increase a degree of integration of a semiconductor at an increased speed. Accordingly, an LSI (large scale integration) circuit has come to have greater size and complexity. On the other hand, a life cycle of an electronic device including the LSI is becoming shorter. Therefore, a circuit design is requested to be completed in a shorter time period. However, known design methods may not design the LSI having the required greater size and complexity effectively. Thus, various EDA (electronic design automation) tools for describing a design at an increased abstract level are proposed.
One example of the EDA tool is a behavioral synthesis tool. The behavioral synthesis tool generates an RTL (register transfer level) description from a behavioral description for describing an operation of hardware. The RTL description is input to a logic synthesis tool. The behavioral description describes an algorithm of processing to be executed by the hardware directly in a motion level, and does not recognize a concept of clock cycles. On the other hand, the RTL description recognizes a concept peculiar to the hardware, such as register and clock synchronism. The behavioral synthesis tool automatically synthesizes the behavioral description into the RTL description to increase the abstract level of the design.
When the behavioral synthesis tool generates the RTL description, a latency in the RTL description needs to be checked. The latency denotes a total number of clock cycles needed to complete processing for total input data. The latency generally varies depending on type of the input data. Therefore, a logic simulation (e.g., an RTL simulation) is performed on the RTL description to calculate the latency based on the simulation result.
When the latency is calculated by performing the RTL simulation, a target function may not finish with a desired latency. In this case, the behavioral description is checked to determine which part of the behavioral description consumes a great number of clock cycles (e.g., which part of the behavioral description has a great latency). However, known methods may not check the behavioral description effectively.